MWSCAS Myril B. Reed Best Paper Award

No.	Year	Year Presented	Author(s)	Title
20^th	1977	1978	W. Kenneth Jenkins	Techniques for High-Precision Digital Filtering with Multiple Microprocessors
21^st	1978	1979	Sung Mo Kang	An Efficient Design of Large-Scale Communication Networks with a Decomposition Technique
22^nd	1979	1980	None	No Winner was Selected for MWSCAS 1979
23^rd	1980	1981	Clement F. Lee and W. Kenneth Jenkins	Switched-capacitor circuit analysis based on modified nodal analysis
24^th	1981	1982	R.L. Geiger and P.E. Allen	Switched Resistor Filters
25^th	1982	1983	Ann Miller Millman	An Application of Computer Graphics to Combat Vehicle Design
26^th	1983	1984	Byeong G. Lee and Alan Willson	All Two-Transistor Circuits Possess at Most Three DC Equilibrium Points
			C.S. Gargour, B. Nowrouzian and V. Ramachandran	Design Biquadratic Stray Insensitive Switched Capacitor Filters Using Unit Delays and Finite Gain Amplifiers as Basic Building Blocks
27^th	1984	1985	M. Odyniec and L.O. Chuo	Synchronization in Nonlinear Circuits
			A.A. Sakia and E.I. El-Masry	Generation of Equivalent Canonical Digital Filters
28^th	1985	1986	G.M Wierzba and J.V. Svobada	A Comparison of Circuits Generated by Op-Amp Relocation
29^th	1986	1987	H.T. Young and K.S. Chao	A Hight-Resolution Twin-Resistor A/D Conversion Technique
30^th	1987	1988	None	No Winner was Selected for MWSCAS 1987
31^st	1988	1989	Allen Yi-Jen Chan and C.Y. Roger Chen	A-Algorithm -- A New Algorithm for Automatic Test Pattern Generation
32^nd	1989	1990	Moncef Gabborig and Edward J. Coyle	Design of Stack Filters with Structural Constrints Under the MRE Criterion
33^rd	1990	1991	Hiroyuki Wasaki and Yoshihiko Morio	A Localized Learning Rule for Analog VLSI Implementation of Neural Networks
34^th	1991	1992	Russ Duren and Behrouz Peikari	A New Neural Network Architecture for Rationally Invariant Object Recognition
35^th	1992	1993	Axel Thomson and Martin M. Booke	A Temperature Stable Current Reference Source with Programmable Output
36^th	1993	1994	Kaining Wang and Anthony N. Michel	Stability of Dynamical Systems Determined by Differential Inequalities with Applications to Nonlinear Circuits
37^th	1994	1995	Andreas Andreou and Kwabena Doahen	A 48,000 Pixel 580,000 Transistor Silicon Retina in Current-Mode Subthreshold CMOS
			Shomit M. Ghosh and Wafsy B. Mikhael	Comparative Evaluations of 2-D Predictor Implementations for Lossless Compression of Images
38^th	1995	1996	A.G. Dempster and M.D. Macleod	Variation of FIR Filter Complexity with Order
39^th	1996	1997	Mark N. Martin, Philippe O. Pouliquen, Andreas G. Andreou and Martin Fraeman	Current-mode Differential Logic Circuits for Low Power Digital Systems
40^th	1997	1998	Celestino A. Corral, Claude S. Lindquist and Peter B. Aronhime	Sensitivity of the Band-Edge Selectivity of Various Classical Filters
41^st	1998	1999	E. Alarcon, M. Ianazzo, J. Madrenas, J.M. Moreno, S. Gomariz, F. Guinjoan and A. Povada	Implementation of an Application-Specific Fuzzy Controller by Means of a Mixed-Signal Sequential Architecture
42^nd	1999	2000	Samuel L. San Gregory, Charles Brothers, and David Gallagher	A Fast Low Power Logarithm Approximation with CMOS VLSI Implementation
43^rd	2000	2001	Asad Azam, Dhinesh Sasidaran, Karl Nelson, Gary Ford, Louis Johnson and Michael Soderstrand	Single-Chip Tunable Heterodyne Notch Filters Implemented in FPGA's
44^th	2001	2002	Henry H. Y. Chan and Dr. Zeljko Zilic	Substrate Coupled Noise Reduction and Active Noise Suppression for Mixed-Signal System-on-a-Chip
45^th	2002	2003	Geoffrey A Williamson and Daniel A. Bailey	Channel Equalization Using Adaptive Subband Filters
46^th	2003	2004	Mr. Alexandre Marsolais, Prof. M. El-Gamal, Prof. M. Sawan	A CMOS Frequency Synthesizer Covering the Lower and Upper Band of 5GHz WLANs
47^th	2004	2005	K. M. Tsui, S. C. Chan and K. W. Tse	Design of Complex-Valued Variable Digital Filters and Its Application to the Realization of Arbitrary Sampling Rate Conversion for Complex Signals
48^th	2005	2006	B. Choubey and S. Collins	Low dark current logarithmic pixels
49^th	2006	2007	Ta-chien Huang and Charles Zukowski	Reconfigurable Digital/Analog Processor Array for the Simulation of Gene Regulatory Networks
50^th	2007	2008	José C. Garcia, J. A. Montiel–Nelson, H. Navarro, J. Sosa, and S. Nooshabadi	High Performance CMOS Symmetric Low Swing to High Swing Converter for On–Chip Interconnects
51^st	2008	2009	No winner selected
52^nd	2009	2010	Niklas Zimmermann, Björn Thorsten Thiel, Renato Negra, and Stefan Heinen	System Architecture of an RF-DAC Based Multi-Standard Transmitter
53^rd	2010	2011	Matthew Turner and John Naber	The Design of a Bi-directional, RFID-based ASIC for Interfacing with SPI Bus Peripherals
54^th	2011	2012	Masaaki Fujii	Adaptive and Interactive ITI Canceller for Inter-Track Asynchronous shingled Write Recording
55^th	2012	2013	Socrates D. Vamvakos, Claude R. Gauther, Chethan Rao, Karthisha Ramoshan Canagasaby Prashant Choudhary, Sanjay Dabral, Shaishav Desai, Mahmudul Hassan, KC. Hsieh, Bendik Kleveland, Gurupada Mandal, Richard Rouse, Ritesh Saraf, Alvin Wang and Ying Cao	A 2.488-11.2 Gb/s Multi-Protocol SerDes in 40 nm Low-Leakage CMOS for FPGA Applications
56^th	2013	2014	Kushal Das and Torsten Lehmann	Mismatch Insensitive Automatic Tuning Control for the Single Electron Transistor Readout Circuit
57^th	2014	2015	Ho Joon Lee, Young-Bin Ki and Kyung Ki Kim	Mismatch Full Custom Implementation of a S-Box Circuit Architecture Using Power Bated PLA Structure
58^th	2015	2016	Areeb Ali, Neelanjana Pal and Peter Levine	CMOS Inpedance Spectroscopy Sensor Array with Synchronous Voltage-to-Frequency and Core Scaling
59^th	2016	2017	Tim Poguntke and Karltheinz Ochs	Linear time-variant system identification using FMCW radar systems
60^th	2017	2018	Hossein Hosseinzadeh, Mihailo Isakov Mustafa Darbi Amad Patooghy Michael Kinsy	Janus: An Uncertain Cache Architecture to Cope With Side Channel Attacks
61^st	2018	2019	TBD	Award will be presented at MWSCAS 2019 in Dallas, TX